Testonica offers several job positions related to HW and SW development primarily in two different categories: a) FPGA development using VHDL/Verilog, b) embedded SW development using C language. We are primarily looking for master students, but other candidates are welcome too.
The delivered solution enables quality evaluation of up to 10Gbit serial buses (PCIe Gen1/2/3, SATA, optical fiber channel, etc) with a help of powerful FPGA-embedded instrumentation technology. The technology is capable to measure Bit-Error Rate (BER) characteristic for high-speed digital data transmission links as well as to plot so-called BER eye diagram. The latter feature directly fits for mass-production testing since allows every manufactured product to be quickly checked for potential problems on high-speed channels.
Today, an average family spends over 50 Euros of hidden costs annually on No-Failure-Found (NFF) investigations - a known problem of an unknown origin. Tomorrow, the electronic engine control system in a car will be dying after three-five years of operation due to CMOS aging. Actions are urgently needed!
Testonica Lab has released universal virtual embedded instrument IP capable to measure frequencies of high-speed clock signals connected to FPGA device. The developed technology offers an easy way of checking frequencies of on-board oscillators without the need of using any kind of external test and measurement equipment. The method does not involve usage of external nail probes or any other means of physical access to oscillator’s pin.
Artur Jutman, 10th of November, Munich, exhibition grounds. "This is absolutely fantastic" - a typical feedback that I pleasantly hear from respected audience as we are displaying our Flash Accelerator IP and accompanyig software at the GOEPEL booth A1.351.
To be correct, GOEPEL electronic, a Jena, Germany based company is displaying the first ChipVORX® product (an ultra fast flash programmer) that we at Testonica Lab have proudly developed in very tight cooperation with GOEPEL electronic's engineers.
GOEPEL electronic, world-class vendor of JTAG/Boundary Scan solutions announces the first product based on its new ChipVORX® technology at the International Test Conference (ITC'2010) in Austin, TX, USA. The new ChipVORX® based embedded instrumentation solution, developed in cooperation with the Tallinn/Estonia based Company Testonica Lab within the frame of the GATE alliance, is structured modularly as a set of ChipVORX® models and intelligent IPs.
At the International Test Conference (ITC'2010) in Austin, TX, USA, GOEPEL electronic, world-class vendor of JTAG/Boundary Scan solutions announces the development of a new ChipVORX® technology enabling support of embedded test instrumentation in connection with JTAG/Boundary Scan.
Testonica Lab has signed a distribution agreement with France/Rennes based company ASTER Technologies. In frames of this agreement Testonica will distribute ASTER products: TestWay and TestWay Express (testability analyzers), QuadView (doc, layout, schematic and virtual schematic viewers, test program quality reports), QUAD (quality adviser), TPQR (Test Program Quality Report), and WildScan (boundary-scan test conversion) on the territory of Baltic states.
In the frames of GOEPEL's GATE™ program Testonica Lab develops processor' models that enable emulation-based test of PCBs.
The set of supported processors for emulation-based board test is now extended by newly delivered model of Freescale i.MX27 processor. i.MX27 is a multimedia applications processor based on ARM926EJ core featuring h.264 D1 hardware codec for high-resolution video processing, an Ethernet 10/100 MAC, security management, plug-and-play connectivity and extended power management.
European Union's 7th Framework Programme's collaborative research project FP7-2009-IST-4-248613 DIAMOND (www.fp7-diamond.eu) - Diagnosis, Error Modelling and Correction for Reliable Systems Design aims at improving the productivity and reliability of semiconductor and electronic systems design in Europe by providing a systematic methodology and an integrated environment for the diagnosis and correction of errors.