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Testonica delivers technology for Marginal Defect detection on DDR3/4 bus

Testonica delivers technology for Marginal Defect detection on DDR3/4 bus

Marginal Defects, such as excessive voids in solder joints, dewetting, head-in-pillow and alike do not necessarily cause malfunctions, but may result in system performance issues, increased error rates, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. As a result, Marginal Defects may lead to No Fault/Trouble Found (NFF/NTF) scenarios.

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IEEE I&M Magazine published our technical paper

IEEE I&M Magazine published our technical paper

In its Aug-Sept issue, IEEE Instrumentation & Measurement Magazine published our technical paper that was originally presented last year at AUTOTESTCON conference in Anaheim, CA. It is one of six conference papers selected for the journal on a quality basis out of the total of 80 AUTOTESTCON'2016 contributions.

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Chairing TESTA workshop in Cyprus

Chairing TESTA workshop in Cyprus

Testonica's director Dr. Artur Jutman serves this year as the General Chair of the 2nd International Test Standards Application Workshop (TESTA'2017). The TESTA workshop is a focused, open discussion platform dedicated to exchange of fresh ideas, industrial best practices, methodologies and work‐in‐progress around test related standards, especially those being actively developed today or the ones recently released.

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Testonica participates in just launched H2020 project IMMORTAL

Testonica participates in just launched H2020 project IMMORTAL

In March 2015, work commenced on a European Union's Horizon 2020 Programme's collaborative research project H2020-ICT-2014-1-644905 IMMORTAL - Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems. In frames of this project, a consortium of leading European academic and industrial players aim at combining their expertise in developing an integrated, cross-layer modeling based tool framework for fault management, verification and reliable design of dependable Cyber-Physical Systems (CPS).

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Testonica is hiring

Testonica is hiring

Testonica offers several job positions related to HW and SW development primarily in two different categories: a) FPGA development using VHDL/Verilog, b) embedded SW development using C language. We are primarily looking for master students, but other candidates are welcome too.

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Testonica delivers embedded Bit-Error Rate Test (BERT) technology

Testonica delivers embedded Bit-Error Rate Test (BERT) technology

The delivered solution enables quality evaluation of up to 10Gbit serial buses (PCIe Gen1/2/3, SATA, optical fiber channel, etc) with a help of powerful FPGA-embedded instrumentation technology. The technology is capable to measure Bit-Error Rate (BER) characteristic for high-speed digital data transmission links as well as to plot so-called BER eye diagram. The latter feature directly fits for mass-production testing since allows every manufactured product to be quickly checked for potential problems on high-speed channels.

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Testonica coordinates just launched FP7 project BASTION

Testonica coordinates just launched FP7 project BASTION

Today, an average family spends over 50 Euros of hidden costs annually on No-Failure-Found (NFF) investigations - a known problem of an unknown origin. Tomorrow, the electronic engine control system in a car will be dying after three-five years of operation due to CMOS aging. Actions are urgently needed!

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Clock frequency measurement using embedded instruments

Clock frequency measurement using embedded instruments

Testonica Lab has released universal virtual embedded instrument IP capable to measure frequencies of high-speed clock signals connected to FPGA device. The developed technology offers an easy way of checking frequencies of on-board oscillators without the need of using any kind of external test and measurement equipment. The method does not involve usage of external nail probes or any other means of physical access to oscillator’s pin.

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ChipVORX® attracts a great attention at Electronica exhibition in Munich

ChipVORX® attracts a great attention at Electronica exhibition in Munich

Artur Jutman, 10th of November, Munich, exhibition grounds. "This is absolutely fantastic" - a typical feedback that I pleasantly hear from respected audience as we are displaying our Flash Accelerator IP and accompanyig software at the GOEPEL booth A1.351.

To be correct, GOEPEL electronic, a Jena, Germany based company is displaying the first ChipVORX® product (an ultra fast flash programmer) that we at Testonica Lab have proudly developed in very tight cooperation with GOEPEL electronic's engineers.

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Embedded ChipVORX® IP Enables Ultra Fast Flash Programming

Embedded ChipVORX® IP Enables Ultra Fast Flash Programming

GOEPEL electronic, world-class vendor of JTAG/Boundary Scan solutions announces the first product based on its new ChipVORX® technology at the International Test Conference (ITC'2010) in Austin, TX, USA. The new ChipVORX® based embedded instrumentation solution, developed in cooperation with the Tallinn/Estonia based Company Testonica Lab within the frame of the GATE alliance, is structured modularly as a set of ChipVORX® models and intelligent IPs.

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