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Testonica delivers technology for Marginal Defect detection on DDR3/4 bus

Testonica delivers technology for Marginal Defect detection on DDR3/4 bus

Marginal Defects, such as excessive voids in solder joints, dewetting, head-in-pillow and alike do not necessarily cause malfunctions, but may result in system performance issues, increased error rates, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. As a result, Marginal Defects may lead to No Fault/Trouble Found (NFF/NTF) scenarios. Marginal Defects on DDR3/DDR4 bus may be easily masked by the mandatory calibration procedure executed periodically on the bus escalating the difficulty of the defect detection challenge.

Testonica has developed a novel technology and respective demonstrator for Marginal Defect detection on DDR3/DDR4 bus. The technology relies on the same calibration mechanism, but executes the calibration in a special mode and uses specific proprietary stimuli. As a result, instead of masking, we are revealing such defects by amplifying their harmful effect on the data stability during the test.

The technology demonstrator is based on a typical Kintex7 FPGA development board with a DDR3 SODIMM slot. The FPGA hosts an Embedded Instrument that contains the standard DDR3 controller and controls the calibration mechanism so that it is measuring operating margins at each DDR3 byte group. Based on these measurements, the software running on an external test equipment performs analysis and detects outliers, which anomalous behavior may be caused by Marginal Defects.

As a proof of concept, we are using two SODIMM memory modules, whereas one is presumably defect-free and the other one has two ground pins intentionally removed. Both SODIMMs correctly function in mission mode (e.g. inside a laptop) including the defective one. However, the Embedded Instrument is still able to differentiate the two pointing out to the reduced operating margin of a particular byte group on the defective SODIMM module. Assuming that the broken ground may not be visible if it is related to soldering quality issues of a memory IC, such a precise diagnosis of Marginal Defects has only been possible using X-Ray or other inspection techniques so far. Now, this new technology can be used as a part of functional test and offered as an option in Automated Test Equipment (ATE) package.

This new technology is one of several breakthroughs achieved in frames of European Commission funded FP7 project BASTION. It has been demonstrated first time during the final project review meeting held in June 2017 in Tallinn and will be presented in October 2017 during the IEEE International Test Conference (ITC'2017) in Fort Worth, TX. A copy of the respective technical paper titled "Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus" is available on request from Testonica Lab.