IEEE1687 IJTAG
We develop advanced solutions for designing scalable test networks and managing embedded instrumentation in complex systems
We specialize in IJTAG (IEEE 1687) technology, providing advanced solutions for designing scalable test networks and managing embedded instrumentation in complex systems. Our expertise includes automated test generation and fault diagnostics, enhancing testing efficiency and reliability.
Offers/Services
Development of test access procedures for IJTAG instruments (Tessent flow): PDL files preparation, retargeting, test pattern generation for ATE/JTAG, test pattern simulation
IJTAG network extraction from HDL design (generation/preparation of top- and component-level ICL files)
IJTAG network insertion into HDL design (provide test access to in-chip DfT structures)
Siemens Tessent®-flow-based IJTAG network design for Advantest System-Level Test® (SLT) technology
Re-use of embedded instruments and IJTAG DFT infrastructure for board and system-level test (via Goepel System CASCON software or in-house tools)
Other IJTAG-related design/development services and consultancies
DfT for board-level test (BScan structures insertion and validation)
PCBA test services (automated embedded functional board test, BScan test, flying probe, test strategy development and optimization, test coverage assessment)
Commercial Projects
IJTAG tool validation toolkit and hardware design
Overview: Reference IJTAG network implementation. More than 30 embedded instruments (general-purpose registers, access to on-chip sensors and peripherals, etc). Multiple hierarchy layers of various interconnection topologies.
Deliverables: HDL sources, ICL/PDL files, simulation environment, scripts for Tessent ® (retargeting, ICL extraction)
Platform: Runs on FPGA development kit
Demonstrator for European Space Agency that uses IJTAG network for collection of chip health status and diagnostic information on more than 1000 embedded monitors as well as for propagation of alert signals in case of in-chip fault detection events
ESA SoC-HEALTH & SoC-HEALTH2 projects
In-House IJTAG tools
Contributions to IJTAG Community
IJTAG benchmarks collection
Contains 24 networks of different complexity
Provided in ICL format, VHDL/PDL/schematic files also available
Available at: https://gitlab.com/IJTAG/benchmarks
Presented at International Test Conference (ITC) 2016.
A. Tsertov et al., "A suite of IEEE 1687 benchmark networks," 2016 IEEE International Test Conference (ITC), Fort Worth, TX, 2016, pp. 1-10.
Research papers
A. Jutman, S. Devadze, K. Shibin, „Effective Scalable IEEE 1687 Instrumentation Network for Fault Management“, in IEEE Design & Test of Computers, 2013, Vol.30, No.5, pp. 26-35.
K. Shibin, S. Devadze, A. Jutman, “Asynchronous fault detection in IEEE P1687 instrument network”, in Proc of IEEE North Atlantic Test Workshop (NATW’2014), Binghamton, NY, USA, May 14-16, 2014.
F. Ghani Zadegan, E. Larsson, A. Jutman, S. Devadze, R. Krenz-Baath, “Design, Verification and Application of IEEE 1687”, in Proc. IEEE 23rd Asian Test Symposium (ATS’2014), Hangzhou, China, Nov. 16-19, 2014, pp 93-100.
A. Tsertov, A. Jutman, S. Devadze, M. Sonza-Reorda, E. Larsson, F. Ghani Zadegan, R. Cantoro, M. Montazeri, R. Krenz-Baath, “A Suite of IEEE 1687 Benchmark Networks” in Proc. of 47th IEEE International Test Conference (ITC’2016), Fort Worth, TX, USA, Nov 15-17, 2016, paper 6.1.
K. Shibin, S. Devadze, A. Jutman, M. Grabmann, R. Pricken, “Health Management for Self-Aware SoCs based on IEEE 1687 Infrastructure”, in IEEE Design & Test: Special Issue on Self-Awareness in SoCs, Vol 34, No. 6, 2017, DOI: 10.1109/MDAT.2017.2750902, pp. 27-35.
A. Tsertov, A. Jutman, K. Shibin, S. Devadze, “IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring” in Proc. of AUTOTESTCON’2018, National Harbor, Maryland, USA, Sept 17-20, 2018, pp. 336-344.
A. Damljanovic, A. Jutman, G. Squillero, A. Tsertov, “Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks” in Proc. of 24th IEEE European Test Symposium (ETS’2019), Baden-Baden, Germany, May 27-31, 2019, pp. 1-6.
A. Damljanovic, A. Jutman, M. Portolan, E. Sanchez, G. Squillero, A. Tsertov, “Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL” in Proc. of 50th IEEE International Test Conference (ITC’2019), Washington DC, USA, Nov 9-15, 2019, pp. 1-8, paper 7.3.