IEEE1687 IJTAG

We develop advanced solutions for designing scalable test networks and managing embedded instrumentation in complex systems

We specialize in IJTAG (IEEE 1687) technology, providing advanced solutions for designing scalable test networks and managing embedded instrumentation in complex systems. Our expertise includes automated test generation and fault diagnostics, enhancing testing efficiency and reliability.

Offers/Services

  • Development of test access procedures for IJTAG instruments (Tessent flow): PDL files preparation, retargeting, test pattern generation for ATE/JTAG, test pattern simulation 

  • IJTAG network extraction from HDL design (generation/preparation of top- and component-level ICL files)

  • IJTAG network insertion into HDL design (provide test access to in-chip DfT structures)

  • Siemens Tessent®-flow-based IJTAG network design for Advantest System-Level Test®  (SLT) technology

  • Re-use of embedded instruments and IJTAG DFT infrastructure for board and system-level test (via Goepel System CASCON software or in-house tools)

  • Other IJTAG-related design/development services and consultancies

  • DfT for board-level test (BScan structures insertion and validation)

  • PCBA test services (automated embedded functional board test, BScan test, flying probe, test strategy development and optimization, test coverage assessment)

Commercial Projects

IJTAG tool validation toolkit and hardware design

Overview: Reference IJTAG network implementation. More than 30 embedded instruments (general-purpose registers, access to on-chip sensors and peripherals, etc). Multiple hierarchy layers of various interconnection topologies. 

Deliverables: HDL sources, ICL/PDL files, simulation environment, scripts for Tessent ® (retargeting, ICL extraction)

Platform: Runs on FPGA development kit

Demonstrator for European Space Agency that uses IJTAG network for collection of chip health status and diagnostic information on more than 1000 embedded monitors as well as for propagation of alert signals in case of in-chip fault detection events

Learn More

ESA SoC-HEALTH & SoC-HEALTH2 projects

In-House IJTAG tools

ICL/PDL parsing, syntax checking, IJTAG network elaboration

API reference

Developers Guide

FAQ

IJTAG is a standard for accessing and controlling embedded instruments inside chips through a scalable, reconfigurable on-chip network — used for test, debug, configuration and health monitoring of complex SoCs and boards.
Classic JTAG (IEEE 1149.1) tests board-level interconnections; IJTAG (IEEE 1687) manages instruments inside the chip. Testonica works with both, using flows such as Siemens Tessent and GOEPEL CASCON.
In the European Space Agency SoC-HEALTH and SoC-HEALTH2 projects, and it maintains a public collection of 24 benchmark IJTAG networks.