Testonica has just received a Certificate of Recognition from Advantest for our work presented at VOICE 2023 Developer Conference (VOICE 2023) which took place last week in Santa Clara, USA. The presentation "Towards native IEEE 1687 (IJTAG) on ATE" describes a project performed in close collaboration with engineers from Advantest aimed at reference IJTAG network implementation on FPGA for tool ecosystem co-validation purposes.

 

The IEEE Std. 1687 offering a flexible mechanism to access embedded instruments through standard I/O ports (eg. JTAG), gains increasing importance in ASIC designs and large SOCs. IJTAG automates handling and improves communication latency especially in large designs due to its retargeting ability that enables a user to conveniently interact with on-chip resources in a user-friendly, yet powerful way using a standardized interface and without concrete IP knowledge.

 

However, as detailed model of the internal network structure and its state must be processed, the benefits come with the price: a complex tool chain generating the actual patterns. The industry-standard pre-compilation of flat patterns is straightforward but eliminates at the same time interactive user cases.

 

In our presentation, we described a prototype consisting of a complete tool chain for natively running PDL commands online on an IC tester. The tester SW interprets the ICL to build a stateful representation of the resulting IJTAG network. When executing PDL commands, the IJTAG access sequence is generated based on network reconstruction and the appropriate read/write operations are executed on the fly on the IC tester. Finally, the network state representation is updated.

 

We evaluated the solution using an Arty A7 FPGA development board mimicking a real ASIC/IC under test. The design contains dozens of different instruments integrated into an IJTAG network with multiple layers of hierarchy and various interconnection topologies. The instrument examples include read/write access to general-purpose registers, control and monitor on-board components (e.g., LEDs, switches), instruments that communicate with FPGA’s built-in resources such as on-chip temperature and voltage sensors or the system controller.

 

The case study has demonstrated that IJTAG-compliant PDL commands can be directly supported at run-time to communicate with the device under test gaining substantial benefits in reliability, user friendliness and performance especially on interactive use-cases executed right on the ATE.

 

The work has been presented by 
Frank Mielke, Advantest

 

The rest of the project team was:
Olaf Pöppe, Advantest
Matthias Sauer, Advantest
Simon Schweizer, Advantest
Sergei Devadze, Testonica
Anton Tsertov, Testonica
Dmitri Mihhailov, Testonica
Konstantin Shibin, Testonica
Artur Jutman, Testonica

 

The VOICE 2023 features a comprehensive technical program focused on leading-edge technologies and future semiconductor industry trends, thought-provoking speakers and an exhibition area.